1. Field of the Invention
The present invention relates to a clock signal extraction apparatus for extracting a clock signal which determines the timing of received data signals. More particularly, the present invention relates to a clock signal extraction circuit for extracting a clock signal from burst data signals.
2. Description of Related Art
When digital signals are received, it is necessary to provide clock signals which determine the timing for receiving the data. Clock signals are sometimes transmitted from the data transmitter, in which case it becomes necessary to provide a separate path for transmitting the clock signals independently from the data signal. Therefore, extraction clock signals are usually generated by a phase locked loop (PLL) circuit.
The conventional PLL circuit has a voltage-controlled oscillator (VCO) which oscillates an extraction clock signal, a divider and a phase comparator which makes a phase comparison between the extraction clock signal and a data signal. The circuit also has a low-pass filter which generates a control voltage signal for the voltage-controlled oscillator from the output of the phase comparator. The voltage-controlled oscillator changes the frequency of the extraction clock signal in response to the voltage represented by the control voltage signal. The output of the voltage controlled oscillator, after being divided by the divider, is input to the phase comparator.
In cases where the data signal and the extraction clock signal divided therefrom exhibit a phase difference and different frequencies, the phase comparator detects this and outputs a control voltage signal. Both frequency and phase matching between the extraction clock signal and the data signal are achieved by repeatedly changing the oscillation frequency to minimize the phase difference at the time of the rise of the data signal.
In a conventional PLL circuit, once the frequency and phase of the extraction clock signal match those of the data signal, the matched state may be maintained almost indefinitely so long as data signals are successive. In cases where the data signals are burst data signals, however, the frequency and phase of the extraction clock signal must be matched to those of the data signal each time the data signal arrives. Here, "burst data signals" means data signals separated by intervening durations of no data signal.
When a period of no data signal changes to a data signal period, if the difference in phase and frequency is large between the extraction clock signal and the transmitted data signal, a rather prolonged time is required for their matching (pull-in time). Therefore, some leading data of the transmitted data signals may fail to be incorporated. Accordingly, it has been contemplated to add dummy data of a length which corresponds to the maximum pull-in time, to top off the data signals. This addition is, however, troublesome in that it causes poor transmission efficiencies because longer pull-in times require greater amounts of dummy data.
Therefore, there have been proposed a variety of processes for shortening the pull-in time when burst data signals are input. For example, Japanese Laid-Open Patent Appln. No. S63-296589 discloses the oscillation of a voltage-controlled oscillator at a frequency close to that of the burst data signals which are expected to arrive, prior to inputting the data signals. This technique allows the difference in frequency at the time of arrival of the data signals to be minimized, thereby shortening the pull-in time.
In addition, conventional PLL circuits operate first by converting the oscillation frequency of the voltage-controlled oscillator for phase matching and then by converting the frequency again for frequency matching with the data signals. Accordingly, even if the voltage-controlled oscillator was oscillating beforehand at a frequency close to that of the data signals, a relatively long time is needed for pulling in the phase lock. Japanese Laid-Open Patent Appln. No. H1-129530 suggests providing a phase shifter in the PLL circuit to sequentially shift the phase and frequency. This PLL circuit shifts only the phase in the beginning, and then, upon arrival of burst data signals, first performs a phase matching using the phase shifter and then performs a frequency matching using the voltage-controlled oscillator.
However, this process whereby a phase matching step using a phase shifter is followed by a frequency matching step using a voltage-controlled oscillator requires a complicated PLL circuit configuration. In addition, in cases where the frequencies are different, the phases deviate when the next data signal rises if only phase matching is performed at the beginning. Thus, the signal cannot be used any longer as the extraction clock signal. Moreover, the later frequency matching using a voltage-controlled oscillator causes deviation of the once-matched phases. In addition, time is necessary for both phase matching using a phase shifter and frequency matching using a voltage-controlled oscillator. This has caused the problem of prolonged pull-in time if the frequencies are different.